Low-Power Branch Prediction

Low-power design has gained much attention recently, especially for computing on batterypowered equipments. Reducing BTB (branch target buffer) accesses is an effective way to reduce processor power consumption, since BTB consumes a significant portion of power in a processor. In this paper, we propose two approaches to reduce BTB accesses. The first approach expects the distance of every two dynamic branch instructions to be a constant n, where n can be statically profiled, and forces BTB to repose for n instructions after a BTB hit. The second approach dynamically predicts the address of the next branch instruction, and accesses BTB only on the predicted address. Multimedia/DSP benchmarks are used in our evaluation. Experimental results show that these methods can potentially reduce 22.033% of all BTB accesses. keywords: low-power, branch prediction, branch target buffer